Power Architecture & PMIC

Intermediate12 min read

Assumes: 0.1 Anatomy of an SoC, 0.3 Memory, Storage & Boot Media

TL;DR

Vehicle power starts at the 12V battery, passes through regulators and protection circuitry, and lands at the PMIC (Power Management IC) — the SoC’s power butler. The PMIC converts messy automotive voltage into a dozen voltage rails, each tuned to a specific domain: CPU core at ~0.8V, memory at ~0.8V, GPU at ~0.5–0.9V, I/O at 1.8V, analog at 1.8V. Every domain gets its own rail. Power sequencing is law: rails must come up in a fixed order (Always-on → Core → Peripherals → I/O) or the chip risks latch-up, brown-out, or permanent damage. Industry rule of thumb: ~70% of first-boot failures trace to power — wrong sequencing, missing bypass caps, or input voltage dipping during engine crank.

You debug boot chains and flash partitions all day, but when a board won’t boot, the first question isn’t “is XBL corrupt?” — it’s “are the rails alive?” Software engineers don’t usually love power electronics, but power electronics doesn’t care about your feelings. This page maps vehicle power from the battery terminal to the millivolt lines feeding your Kryo cores.

Vehicle Power System Overview

Automotive electrical systems are not a clean 12V DC source. They’re a noisy, spiky, temperature-dependent supply that the SoC must never see directly.

Rail	Nominal	Real-World Range	Context
12V LV	12V	9V (cranking) → 16V (jump-start)	Primary supply for infotainment ECU
48V mild hybrid	48V	36V–54V	Start-stop, e-compressor, some DC-DC feeds
HV (EV)	400V+	Pack-dependent	Powers traction; cockpit gets isolated 12V via DC-DC

Mnemonic: “12V is marketing. 14.4V is charging. 9V is cranking.”

When the engine is running, the alternator holds the bus around 13.5–14.4V — not 12V. During cranking, the starter pulls hundreds of amps and the bus can sag to 9V for 100–300 ms. A jump-start from another vehicle can push 16V briefly. Your cockpit ECU sits behind fuses, reverse-polarity protection, and often a pre-regulator (12V → 5V or 3.3V) before the PMIC ever sees the input.

Why the SoC never sees 12V directly: The Kryo CPU core runs at ~0.65–0.9V. Feeding 12V into a billion transistors designed for sub-1V would vaporize the die in microseconds. Even if it didn’t, a single-stage 12V→0.8V conversion at the currents a modern SoC demands (tens of amps on the core rail) would be thermally absurd. The PMIC exists to step down, split, sequence, and monitor — turning automotive chaos into the stable millivolt diet each domain requires.

Mental Model

The PMIC is a power plant with very opinionated transformers. The 12V “high-voltage line” from the vehicle arrives at the plant gate — messy, spiky, and about as stable as WiFi on a train. Inside, multiple substations (buck converters and LDOs) each produce exactly the voltage one district needs. VDD_CX is the CPU district — city hall, where QNX and AAOS run. VDD_MX is the memory district — the warehouse (LPDDR) next door. VDD_GFX is the GPU district — the billboard factory painting pixels. VDD_IO and VDDA_1P8 are the utility districts — streetlights and sensors at a higher, safer voltage. Flip the wrong substation first and the whole grid collapses — which is why the PMIC has a strict startup playlist it will not negotiate on.

PMIC Deep Dive

On Qualcomm cockpit platforms, the PMIC is typically a companion chip on the board — for SA8155P-class designs, think PM8150 (or PM8150A/B variants in the same family). The exact part number varies by OEM BOM, but the architecture is consistent: one PMIC (sometimes two for larger rails) serves the application processor.

Buck Converters vs LDOs

Type	How It Works	Efficiency	Noise	Typical Use
Buck (step-down switcher)	Switched inductor, PWM control	High (85–95%)	Higher ripple; needs good caps	High-current rails: VDD_CX, VDD_MX, VDD_GFX
LDO (Low Drop-Out linear)	Transistor drops excess voltage as heat	Lower (wastes heat on large ΔV)	Very low noise	Analog, sensitive I/O, small current rails

Rule of thumb: Bucks feed the hungry districts (CPU, GPU, memory). LDOs feed the picky ones (analog front-end, reference voltages, low-noise sensors).

Key Voltage Rails

Rail	Typical Voltage	Domain	Notes
VDD_CX	0.65–0.9V (DVFS)	CPU core (Kryo)	Highest current; scales with frequency/load
VDD_MX	0.65–0.9V	Memory interface, logic	Paired with LPDDR I/O
VDD_GFX	0.5–0.9V	GPU (Adreno)	Spikes during 3D rendering
VDDA_1P8	1.8V fixed	Analog (audio codec, ADC refs)	LDO-fed, noise-sensitive
VDD_IO	1.8V / 3.3V	GPIO, I2C, SPI, some USB	Must come after core rails

flowchart LR
    BAT["Vehicle 12V<br/>9V–16V"]
    PRE["Pre-Regulator<br/>12V → 5V"]
    PMIC["PMIC (e.g. PM8150)"]

    subgraph BUCKS["Buck Converters — high current"]
        CX["VDD_CX<br/>~0.8V · CPU"]
        MX["VDD_MX<br/>~0.8V · Memory"]
        GFX["VDD_GFX<br/>~0.7V · GPU"]
    end

    subgraph LDOS["LDOs — low noise"]
        A18["VDDA_1P8<br/>1.8V · Analog"]
        IO["VDD_IO<br/>1.8V · I/O"]
    end

    SOC["Qualcomm Cockpit SoC<br/>SA8155P / SA8295P"]

    BAT --> PRE --> PMIC
    PMIC --> CX --> SOC
    PMIC --> MX --> SOC
    PMIC --> GFX --> SOC
    PMIC --> A18 --> SOC
    PMIC --> IO --> SOC

Think About It

Before reading on: your board boots fine on the bench with a stable 12V supply, but dies in the car during engine crank. The 12V rail dips to 9V for 200 ms. Your manager says “it’s a software issue.” What actually fails first — and where do you probe to politely prove them wrong?

Reveal Answer

The PMIC input drops below UVLO (under-voltage lockout) during the 9V crank sag, core rails (VDD_CX/VDD_MX) collapse, and POR (power-on reset) fires before PBL completes — or mid-execution, killing the boot chain. Bench supplies don’t replicate ISO 7637 crank profiles. Probe 12V at the ECU connector during crank with a scope (not a multimeter), then PMIC input post pre-regulator and VDD_CX for rail collapse — before opening QFIL or blaming XBL.

Power Sequencing: The Law

Rails don’t all enable at once. The PMIC follows a hardware-defined sequence baked into its power controller. There is no negotiation. There is no “can we skip this step for faster boot.” There is only the sequence.

Always-On → Core → Peripherals → I/O

Mnemonic: “ACPI” — Always-on, Core, Peripherals, I/O.

Phase	Rails	Purpose
Always-on (A)	RTC, PMIC logic, AOP wake	Keeps time, wake sources, PMIC itself alive in sleep
Core (C)	VDD_CX, VDD_MX	CPU and memory can initialize
Peripherals (P)	Display, PCIe, USB PHY power	High-bandwidth blocks after core is stable
I/O (I)	VDD_IO, GPIO banks	External pins become active last

Why sequence matters:

1. Capacitor inrush — Enabling all rails simultaneously causes a current spike that collapses the input voltage.
2. Latch-up risk — I/O pins powered before the core can leave inputs in a safe state → parasitic SCR structures conduct → permanent damage.
3. ESD vulnerability — Live I/O on an unpowered core domain creates current paths through protection diodes into floating logic.

sequenceDiagram
    participant BAT as 12V Input
    participant PMIC as PMIC Controller
    participant AON as Always-On Rail
    participant CORE as VDD_CX / VDD_MX
    participant PERI as Peripheral Rails
    participant IO as VDD_IO

    BAT->>PMIC: Input stable (> UVLO)
    PMIC->>AON: Enable (t=0 ms)
    Note over AON: RTC, wake, PMIC logic
    PMIC->>CORE: Enable (t=1–5 ms)
    Note over CORE: POR releases when core > threshold
    PMIC->>PERI: Enable (t=5–15 ms)
    Note over PERI: USB, display, PCIe PHY
    PMIC->>IO: Enable (t=15–20 ms)
    Note over IO: GPIO safe — core is running

POR and Brown-Out Detection

POR (Power-On Reset) holds the SoC in reset until core rails exceed a minimum threshold for a debounce period (microseconds to milliseconds). If VDD_CX dips below the brown-out threshold even briefly, POR re-asserts and the boot chain restarts from ROM — or hangs if the dip is intermittent.

Brown-out detection is the PMIC’s watchdog on rail quality. A 50 µs dip below threshold is enough to kill PBL mid-execution. This is not hypothetical — it’s the root cause in the war story below.

Common Gotcha

“12V goes straight to the SoC.” If you hear someone say this, hand them this page. The SoC core runs at ~0.8V. A single-stage 12V→0.8V step-down at 10+ amps would be ~6% efficient and would turn the board into a space heater. PMICs use multi-stage conversion: 12V→5V→0.8V or 12V→3.3V→0.8V, with each stage operating in its efficient range. Direct 12V to the SoC would destroy the die in microseconds — the PMIC exists specifically to prevent that extremely expensive mistake.

Common Gotcha

If you power the I/O rail before the core rail, you risk latch-up. This is not a theoretical concern — it’s the kind of bug that turns a prototype into a paperweight and a BOM line item into a replacement order.

I/O pins become active while internal logic is still off. Current injects through ESD protection diodes into floating transistors, triggering parasitic thyristors. Current rushes through unintended paths; the chip may latch permanently (only power-cycle or scrap fixes it). This is why ACPI sequencing is hardware-enforced, not a software preference — the silicon learned this lesson so you don’t have to.

Power Domains in Practice

Qualcomm cockpit SoCs partition power into domains the PMIC and firmware manage independently:

Domain	Contents	Sleep Behavior
Always-on	RTC, PMIC SPMI, AOP, wake GPIO	Stays powered in STR (suspend-to-RAM)
Active (Apps)	Kryo CPU, Adreno GPU, Hexagon DSP	Gated by cpufreq / devfreq; rails scale with load
Modem	Separate baseband subsystem	Semi-independent PMIC path; PIL loads firmware
Peripheral	USB, PCIe, display PHY, UFS	Powered down in deep sleep; sequenced on wake

When you see “the board is in sleep but telematics still wakes,” that’s the always-on domain doing its job. When the cluster animates but the modem is off, that’s domain gating — not a bug.

PMIC Register-Level: SPMI, PON, and Rail Readback

The PMIC communicates with the SoC over SPMI (System Power Management Interface) — a low-speed serial bus (similar in role to I2C) used for rail control, status readback, and interrupt signaling. QNX and the boot firmware read PMIC registers during bring-up.

Key registers you’ll encounter in BSP docs and crash logs:

• PON (Power-On) reason register — Records why the chip last powered on: cold boot (first power application), warm reset (software reset), watchdog reset, key press, USB insert, RTC alarm. QNX reads PON during early init to distinguish cold boot vs warm boot vs watchdog recovery and adjust logging or recovery paths.
• Voltage rail readback — SPMI reads confirm each rail is within tolerance. Factory tests and debug scripts sweep these before trusting PBL output.
• PMIC watchdog timer — If the AP hangs without petting the PMIC watchdog, the PMIC power-cycles the SoC. PON reason shows WDOG — invaluable when the symptom is “reboots every 30 seconds with no crash dump.”

You won’t write SPMI drivers daily, but when PBL succeeds and XBL dies with no UART output, a rail readback log from the PMIC often beats hours of partition forensics.

Where You'll See This

Symptom mapping: Board won’t boot → check power first, always. Before opening QFIL or blaming XBL:

1. 12V input at the ECU connector — is it present? Does it sag under load?
2. PMIC input (post pre-regulator) — typically 5V or 3.3V; confirm within datasheet range
3. Each output rail — VDD_CX, VDD_MX, VDD_GFX, VDD_IO, VDDA_1P8 — in sequencing order

Use a multimeter for DC levels; use a scope for crank dip and ripple on VDD_CX. A rail that reads 0.82V on a meter but dips to 0.55V for 50 µs during load steps will fail POR intermittently — the meter lies; the scope doesn’t.

War story: A tier-1 supplier had 200 boards that intermittently failed PBL on cold start (-30°C chamber). UART showed nothing — not even PBL banner. Every partition and flash was verified good. Oscilloscope on VDD_CX revealed a 50 µs dip below POR threshold during rail ramp. Root cause: a 22 µF bypass cap on VDD_CX had the right capacitance but wrong ESR spec for the PMIC’s transient response. Under cold start, ESR rose enough to let the rail sag. Fix: change capacitor vendor (same value, correct ESR rating). 200 boards recovered without a single line of software changed.

When someone says “it boots on the bench but not in the vehicle,” your first probe is the 12V input during crank, not the partition map.

Connect the Dots

Page 5.2 (The Boot Chain): PBL only runs after power sequencing completes and POR releases — if rails aren’t stable, you never reach XBL. Page 6.5 (Power Management Across VMs): OS-level power states (ACC / RUN / CRANK / SLEEP) map to PMIC rail enables and domain gating across QNX and AAOS guests. Page 10.1 (The Debug Bench): First step of board bring-up is always power rail verification — before UART, before USB, before QFIL.

The short version

1. Vehicle 12V is really 9V–16V. The SoC sees sub-1V rails from the PMIC, never battery voltage.
2. PMIC = power butler: bucks for high current, LDOs for low noise, strict ACPI sequencing.
3. Wrong sequence or bad bypass caps → POR failures, latch-up, or intermittent PBL death.
4. Board won’t boot? Multimeter the rails in order before you flash anything.

Check Your Understanding

1. Why does the SoC need a PMIC instead of direct 12V from the vehicle battery?

Recall

A. The PMIC stores energy in supercapacitors to ride through cranking dips without rail dropoutB. Direct 12V works but violates ISO 26262 unless a PMIC is inserted for safety certificationC. The SoC needs multiple sub-1V rails converted, sequenced, and monitored from the noisy 12V supplyD. Qualcomm PMICs include integrated UFS storage that holds the XBL boot chain on-chip

2. What is the correct power sequencing order for SoC rails?

Recall

A. Always-on → Core → Peripherals → I/O — ACPI order prevents latch-up and inrush damageB. Core first, then I/O, then Always-on, then Peripherals — CPU must boot before anythingC. I/O first, then Core, then Peripherals, then Always-on — external pins need priorityD. All rails enable simultaneously to minimize total boot time and reach PBL faster

3. A board boots on the bench but dies during engine crank. Most likely cause?

Applied

A. PMIC input drops below UVLO during crank sag, collapsing core rails and triggering PORB. XBL partition corruption caused by mechanical vibration during engine start-upC. Android A/B slot mismatch triggered by voltage fluctuation during the crank windowD. UFS LUN 0 bootloader wear-out from excessive cold temperature read-write cycles

4. VDD_CX reads 0.82V on a multimeter but the board intermittently fails POR during load steps. A scope reveals 50 µs dips to 0.55V. Most likely root cause?

Applied

A. Bypass capacitor with wrong ESR — the meter shows average, not the transient sagB. CAN transceiver drawing excess current from VDD_IO and pulling down adjacent railsC. Corrupted XBL partition causing the firmware to shut down the rail prematurelyD. Wrong UFS LUN selected during the most recent QFIL flash and partition write

5. Which PMIC rail typically feeds the Kryo CPU core cluster?

Recall

A. VDD_CX at 0.65-0.9V, dynamically scaled via DVFS as Kryo frequency changesB. VDD_GFX for the Adreno GPU — CPU and GPU share a single high-current power railC. VDDA_1P8 for analog references — the CPU core uses the same clean analog supplyD. VDD_IO at 1.8V, shared between the CPU core and the external GPIO banks

6. UART shows XBL banner then silence on cold crank at −30°C, but the same board boots cleanly on a stable 12V bench supply. PON reason register reads cold boot followed by watchdog reset. Partition integrity is verified. What validation gap and boot-chain interaction explain this?

Synthesis

Connects to: Module 5 — Boot Chain · Module 8 — Build, Flash & Update

A. UFS read latency exceeds XBL timeout at cold temperature — need a faster flash chipB. TrustZone secure boot signature verification only fails below 0°C due to timing marginsC. Crank sag trips PMIC UVLO mid-boot — bench supply masks ISO 7637 transients that vehicles presentD. LPDDR4 refresh rate is too slow at −30°C, causing the Android kernel load to fail

Further Reading

• Qualcomm SA8155P Product Brief (PDF) — Documents the PM8150 companion PMIC, voltage rails, and power/thermal specs paired with Snapdragon cockpit SoCs.
• MIPI Alliance — System Power Management Interface (SPMI) — Serial bus specification used for PMIC-to-SoC communication, rail control, and PON reason register readback.
• ISO 7637-2 — Road vehicles — Electrical transient conduction along supply lines — Defines cranking dips, load dump, and other 12V transients that PMIC input stages must survive.
• Texas Instruments — Power Management IC Design Guide — Vendor resource hub for buck/LDO design, sequencing, and bypass capacitor selection principles applicable to automotive PMIC layouts.
• Analog Devices — Power System Management Fundamentals — Technical article series on power sequencing, brown-out detection, and rail monitoring concepts mirrored in ACPI ordering.
• AEC-Q100 — Failure Mechanism Based Stress Test Qualification for Integrated Circuits — Automotive IC qualification including PMIC temperature, voltage, and reliability stress requirements.
• Fundamentals of Power Electronics (Erickson & Maksimović, Springer) — Graduate-level textbook on switched-mode power conversion theory underlying buck converter design in PMICs.